The present invention relates to a semiconductor device; and, more particularly, to a method for manufacturing a semiconductor memory device incorporating therein textured electrodes for implementing a high-density storage capacitor.
As is well known, a dynamic random access memory (DRAM) with at least one memory cell comprised of a transistor and a capacitor has a higher degree of integration mainly by downsizing through micronization. However, there is still a demand for downsizing the area of the memory cell.
To meet the demand, therefore, there have been proposed several methods, such as a trench type or a stack type capacitor, which is arranged three-dimensionally in a memory device to reduce the cell area available to the capacitor. However, the process of manufacturing three-dimensionally arranged capacitor is a long and tedious one and consequently involves high manufacturing cost. Therefore, there is a strong demand for a new memory device that can reduce the cell area with securing a requisite volume of information without requiring complex manufacturing steps.
In attempt to meet the demand, there have been proposed a high-density dynamic random access memory (DRAM) which incorporates bottom electrodes having textured surface morphology by forming hemispherical grain (HSG) thereon.
One of the major shortcomings of the above-described high-density DRAM is that it requires processes for forming a nitride layer and a buffer oxide layer as an etching stop layer during the formation of the bottom electrodes.
It is, therefore, an object of the present invention to provide a method for manufacturing a semiconductor device capable of simplifying the manufacturing steps thereof by incorporating therein a carbon layer as a supporting layer.
In accordance with one aspect of the present invention, there is provided a method for manufacturing a semiconductor device for use in a memory cell, the method comprising the steps of: a) preparing an active matrix provided with at least one transistor, a plurality of conductive plugs electrically connected to the transistors and an insulating layer formed around the conductive plugs; b) forming a supporting layer, made of carbon, on top of the active matrix and patterned into a predetermined configuration, thereby obtaining a patterned supporting layer; c) forming bottom electrodes on the patterned supporting layer; d) removing the patterned supporting layer; e) forming hemispherical grains (HSGs) on surfaces of the bottom electrodes; f) forming capacitor dielectric films on top of the bottom electrodes; and g) forming top electrodes on top of the capacitor dielectric films, thereby obtaining a capacitor.